A semiconductor integrated circuit device equipped with a read-only memory function capable of rewriting data by ultraviolet rays (hereinafter called "EPROM") is known. A memory cell for storing data in an EPROM consists of a field effect transistor equipped with a floating gate disposed on a semiconductor substrate via a first insulating layer and a control gate disposed on the floating gate via a second insulating layer. Generally, both floating and control gates consist of polycrystalline silicon (Refer, for example, to the magazine "Nikkei Electronics", Jan. 5, 1981, pp. 181-201.)
It is possible in principle to cover sides of both the floating and control gate with a compact silicon oxide layer formed by thermal oxidation techniques in order to improve the retention characteristics of the charge, as the data, stored in the floating gate. This is necessary to limit the reduction of the stored charge due to leakage that develops between the edge portion of the floating gate and the source-drain region or the control gate.
As a result of experiments and studies on such technique, the inventors of the present invention have found out the fact that the retention characteristics of charge, as the data, stored in the floating gate can be improved by covering both floating and control gates with a compact silicon oxide layer, formed by thermal oxidation, having a film thickness equal to, or greater than, the film thickness of the first insulating layer.
The inventors believe, however, that such a compact silicon oxide layer having a film thickness equal to, or greater than, the film thickness of the first insulating layer is contradictory to the miniaturization of the memory device for the following reasons.
With the miniaturization of the EPROM, memory cell reliability and operating speed drop in the data write and read modes. On the other hand, a heat-treatment step for an extended period of time is necessary in order to obtain a desired film thickness for the compact silicon oxide layer. The forming speed of the silicon oxide layer between the floating gate and the control gate is higher than the forming speed of the silicon oxide layer between the floating gate and the semiconductor substrate. Moreover, the forming speed of the silicon oxide layers are higher at the edge portions of the surfaces of the floating and control gates than that on the main surface of the semiconductor substrate. Accordingly, lift-up occurs, particularly at the edge of the control gate. This means that in comparison with the parasitic capacitance formed by the former, the parasitic capacitance formed by the latter is bigger. Thus, the potential of the floating gate drops with the result that the efficiency as well as reliability drop in the write mode of the data to the memory cell. In the data read mode from the memory cell, on the other hand, the quantity of current that flows through the channel region between the source and drain regions becomes smaller. This makes it difficult to rapidly discharge the charge that is charged in a data line, and invites the drop of the speed. The shorter the channel length, the more remarkable this phenomenon, because the proportion of the capacitance drop becomes greater This creates a problem for the miniaturization of the memory cell.
The source or drain region of the field effect transistor to serve as the memory cell is formed in the following way. An impurity for forming the region is introduced by ion implantation into the main surface of the semiconductor substrate on both sides of the floating and control gates using these gates as the mask. Thereafter, the compact silicon oxide layer is formed, and the impurity is subjected to drive-in diffusion. In this case, since the heat-treatment step for a long period is necessary as described above, the effective channel length between the source and drain regions becomes shorter because drive-in diffusion is effected excessively. This induces the short channel effect, invites a drop in reliability of the EPROM in the data read and write modes, and is unsuitable for the scale-down of the memory cell.